The ability of metal-oxide-semiconductor (MOS) devices to store information in non-volatile binary form is well known. Typically, non-volatile MOS storage devices employ a completely insulated or floating conductive gate overlying an active substrate region such that charge carriers can be transferred between the floating gate and the active substrate region during device program and erase operations. The program operation of many early MOS floating gate storage devices in particular is performed using electron injection mechanisms. For example, the double polycrystalline silicon gate storage device disclosed in U.S. Pat. No. 3,996,657 issued to Simko et al on Dec. 14, 1976 is programmed by applying a positive potential to a storage device control gate vertically-aligned with the storage device floating gate, whereupon hot carrier injection of electrons from the channel region of the storage device through the gate oxide to the floating gate occurs. In contrast to the relatively simple electrical programming procedures associated therewith, however, devices of the type disclosed in the aforementioned Simko et al patent are cumbersome to erase, usually requiring the application of ultraviolet radiation or the use of relatively large voltage potentials to remove charge carriers from the floating gate.
More recent developments in MOS memory cell technology have focussed on storage devices which lend themselves to electrical erasing as well as electrical programming. U.S. Pat. No. 3,919,711 issued to Chou on Nov. 11, 1975, and U.S. Pat. No. 4,087,795 issued to Rossler on May 2, 1978 both disclose storage devices having floating gate structures which are electrically charged via an injection mechanism during programming operations and electrically discharged via a tunneling mechanism during erasing operations. Tunneling in the Chou and Rossler devices nevertheless takes place through a relatively thick gate oxide layer (i.e., between 200A and 500A), and the high erasing potentials consequently required to discharge the floating gate restrict the commercial applicability of such structures.
The advent of thin gate oxides has to a great extent alleviated many of the complexities associated with previous MOS floating gate storage devices. U.S. Pat. No. 4,115,914 issued to Harari on Sept. 26, 1978; U.S. Pat. No. 4,203,158 issued to Frohman-Bentchkowsky et al on May 13, 1980 and Japanese Patent Application No. Sho 52-32359 by Iwamatsu all illustrate floating gate storage devices wherein a portion of the gate oxide is reduced in thickness to provide a thin tunnel dielectric through which charge carriers may enter or leave the floating gate. FIG. 1 is a cross-sectional view of a representative prior art floating gate storage device, and more specifically depicts one embodiment of the storage device disclosed in the aforementioned Frohman-Bentchkowsky et al patent. Prior art storage device 2 is fabricated on a p-type silicon substrate 4. Spaced-apart n-type source and drain regions 6, 8 are formed in substrate 4, while an electrically floating polycrystalline silicon gate 10 and a second or program gate 12 also formed from polycrystalline silicon are disposed in vertical alignment above the channel 14 defined by the source and drain regions 6, 8. As discussed above, gate 10 is electrically floating, and hence is completely surrounded by an insulating material comprised of a gate oxide layer 16 and an interpoly oxide layer 18. Interpoly oxide layer 18 has a generally uniform thickness somewhere in the range between 500A and 1,000A. Similarly, most of the gate oxide layer 16 separating floating gate 10 from substrate 4 is between 500A and 1,000A in thickness, but in contrast to the interpoly oxide layer 18, gate oxide layer 16 contains a relatively thin portion 20 overlying an n-type substrate tunneling region 22 contiguous with source region 6. This relatively thin portion or tunnel dielectric 20, which is on the order of 70A-200A in thickness, facilitates the tunneling of electrons into and out of floating gate 10. That is, when a positive potential of approximately 20 volts is applied to program gate 12 via lead 24, an electrical field of sufficient magnitude to tunnel electrons from tunneling region 22 to floating gate 10 is established, whereas the application of a positive 20 volt potential to source region 6 via lead 26, in combination with the grounding of program gate 12, establishes an electrical field of sufficient magnitude and direction to tunnel electrons back from floating gate 10 into tunneling region 22. The corresponding change in threshold voltage of memory device 2 as electrons are tunneled into and out of floating gate 10 affects the conductive qualities of channel region 14, thus providing a means to sense the presence or absence of charge on floating gate 10 by application of suitable potentials to program gate 12 and subsequent measurement of current flow between the source and drain regions 6 and 8.
The prior art device of FIG. 1 may be incorporated into a memory cell and employed in a large-scale integrated circuit array such as a programmable read-only memory or PROM. A prior art memory cell 28 constructed in accordance with the teachings of the aforementioned Frohman-Bentchkowsky et al patent is shown in FIG. 2. Memory cell 28 includes a storage device 30 connected in series with a field effect transistor 32. Storage device 30 is similar to the storage device 2 illustrated in FIG. 1, except that the substrate tunneling region (not shown in FIG. 2) associated with storage device 30 is now contiguous with the storage device drain region 34 as opposed to the storage device source region 35. Storage device source region 35 is in turn grounded, as indicated at 36, while the program gate 37 of storage device 30 is connected to a program select line 38. Field effect transistor 32 serves as a selection transistor, and to this end the control gate 39 of the field effect transistor is connected to a word select line 40 while the drain of the field effect transistor is connected to a metallic column line 41 via metal contact 42. When storage device 30 is to be programmed, column line 41 is grounded and a potential is supplied to word select line 40, bringing transistor 30 into conduction and transferring ground potential from column line 41 to the drain region 34 of storage device 30. A positive potential of 18 to 24 volts is then applied to program select line 38, causing charge carriers to transfer from the storage device tunneling region through a thin oxide (not shown in FIG. 2) to the storage device floating gate 43. Erasing is accomplished by grounding program select line 38 and applying a relatively high potential, i.e., 18 volts, to column line 41 in order to transfer the column line potential to the storage device drain region 34. Charge carriers then tunnel back through the storage device thin oxide into the storage device tunneling region contiguous with drain region 34. When the status of storage device 30 is to be read, the potential of word select line 40 is once again raised until field effect transistor 32 conducts. Thereafter, a potential V applied from column line 41 through transistor 32 to the drain region 34 of storage device 30 will produce current flow through the channel region of the storage device only if charge carriers have been removed from the storage device floating gate. In this manner, the presence or absence of charge on the floating gate may be readily determined to provide a binary representation suitable for subsequent PROM manipulations.
The advantages of prior art storage devices of the type illustrated in FIGS. 1 and 2 are obvious. Use of a substrate tunneling region together with a thin tunnel dielectric to transport charges to and from a storage device floating gate enables programming and erasing operations to be performed with a single polarity power source. Moreover, restricting the size of the tunnel dielectric overlying the substrate tunneling region to a small fraction of the overall gate oxide layer materially reduces the difficulties encountered during fabrication of the tunnel dielectric. Despite these advantages, however, room for improvement in the prior art approaches embodied in FIGS. 1 and 2 remains. The tunnel dielectric itself may as a practical matter be less efficient than desired in promoting tunneling, inasmuch as prior art storage devices generally employ tunnel dielectrics consisting of pure silicon dioxide. The potential barrier presented to tunneling charge carriers by the silicon dioxide is relatively large, causing a reduction in tunneling current through the dielectric as the storage device is programmed or erased. It is also more difficult to minimize trapping of charge carriers within the interstitial spaces of silicon dioxide, and the number of program/erase cycles obtainable from a device having a tunnel dielectric formed from silicon dioxide is correspondingly decreased. Additional problems are created in prior art storage devices exhibiting a contiguous relationship between the substrate tunneling region and other active substrate regions, i.e., the storage device source region or the storage device drain region. Such a relationship limits the flexibility otherwise available in selecting optimum voltages for application to the storage device source or drain regions and the substrate tunneling region. Returning to FIG. 2, it can be seen that a reduced potential V.sub.d, which is less than the full potential V on column line 41 by an amount equal to the threshold voltage V.sub.T of field effect transistor 32, appears in the drain region 34 of storage device 30, and hence in the substrate tunneling region contiguous thereto, when field effect transistor 32 is activated. During read operations, this reduced potential V.sub.d causes "read disturb" conditions to appear in the tunnel dielectric overlying the substrate tunneling region, leading to a decrease in the overall number of read cycles obtainable from memory cell 28. During both programming and erasing of the memory cell, the fact that potential V.sub.d as applied to the substrate tunneling region is reduced from the true or full write line voltage V lowers the efficiency of the program and erase operations. Finally, where prior art memory cells include a direct ground such as ground 36 in the storage device 30 of FIG. 2, a parasitic direct current path through the storage device to ground is created whenever the threshold voltage of the storage device is negative, i.e., whenever the storage device is erased, and the charge pump circuits heretofore utilized in conjunction with prior art memory cells to provide the necessary storage device operating voltages are generally incapable of sustaining this direct current flow. As a net result, the prior art has not been able to fully realize the benefits available from the use of tunneling mechanism in MOS storage devices.